1. Technical Field
This invention relates generally to the manufacture of integrated circuit (IC) chips and, more specifically, to a method for suppressing pattern distortion associated with the reflow of borophosphosilicate glass (BPSG) dielectric layers during the annealing process of subsequent layers.
2. Background Art
In the present era of very large scale integration and ultra large scale integration, new techniques are continuously being developed to more efficiently utilize the space within semi-conductor devices while maintaining or improving present production efficiency, i.e., reducing the number of IC chips that fail because of various mistakes that may occur during the production process.
In the manufacture of IC chips, interconnecting contacts are provided between the active semiconductive material, in which the semiconductor devices are formed, and the interconnect lines. These contacts are typically formed by initially depositing a borophosphosilicate glass (BPSG) dielectric layer over the semiconductor devices. The BPSG material is chosen because it is an acceptable insulator that is capable of being flowed over the devices. The flowability of the material is necessary because the devices present a relatively high aspect ratio and all areas between the devices must be filled without the formation of voids. It was noted early on that BPSG, after reflow, filled a higher proportion of voids than other insulative materials.
The contacts and interconnects are formed by using a dual damascene process. A semi-conductor substrate having devices such as field effect transistors, gates and diodes is provided. The BPSG is deposited over the substrate and associated topography, reflowed to fill high aspect ratio features, then planarized with a chemical-mechanical polish (CMP). A low temperature oxide layer is deposited over the BPSG layer and serves as a polish stop during patterning of subsequent metal layers. A masking layer of photoresist is then provided over the oxide and patterned for exposing the underlying oxide in the contact areas. The exposed oxide and BPSG is then etched, forming contact holes. A second masking layer is provided over the oxide and patterned for exposing the underlying oxide in the interconnect areas. The exposed oxide is then etched, forming troughs for the interconnects. Conducting layers such as aluminum or tungsten are deposited over the wafer by non-selective deposition filling the holes and troughs. The conducting layer is then patterned by CMP to simultaneously form interconnects and contacts.
In a similar fashion, junctions are self-aligned with the contacts by performing the implantation step after the contacts have been etched but prior to the deposition of the conducting layer. The implantation typically involves a high energy ion implant and a high temperature anneal.
A problem with this approach is that distortion of the first contact and interconnect levels can occur during the high temperature junction activation anneal, due to shrinkage of the low temperature oxide and reflow of the BPSG. This distortion can lead to misalignment with subsequent contact levels (which can cause opens or shorts) and variations in interconnect resistance.
It is an advantage of the present invention that mis-alignment problems and variations in resistance are reduced. This reduction is achieved by subjecting the BPSG and undoped oxide to a high temperature before the patterning of the lines, the etching of the contacts and the ion implantation steps. This causes the BPSG and the overlying oxide to densify prior to patterning. Therefore, the shrinkage occurs before the pattern is formed and results in straighter lines which will then be more easily alignable with subsequent layers.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention, the figures and the appended claims.